For circuits which receive independently generated signals, there is often a need to synchronize the reference clock of the receiving circuit with the timing of the incoming signal. This synchronization is generally accomplished by measuring the phase of the incoming signal with reference to the reference clock of the receiving circuit and adjusting the reference clock so that it will approach operating in perfect phase with the incoming signal. Circuits which accomplish this task are called phase-locked loops.
Assuring that the incoming signal is in phase with the reference clock is particularly important in telecommunications circuits which receive bipolar codes. By keeping the phase of the reference clock locked to that of the incoming signal, the circuit assures that the bipolar code received by the telecommunications circuit will be sampled during the optimum portion of each bit period. Typically, such circuits include a reference clock which counts at a frequency which is a multiple of the frequency of the incoming bipolar code signal. The circuit detects when the bipolar code crosses the zero voltage level and adjusts the counter of the reference clock so that it begins counting close to that point.
Because the bipolar code may be received slightly distorted due to intersymbol interference which may cause more or less than one zero crossing per bit period, or due to "ringing" caused by overshoot, or the like which leads to multiple zero crossings during a single bit period, the phaselocked loop may generate clock jitter as it attempts to lock on to the phase of the incoming signal during these distortions.
For instance, FIG. 1 shows a bipolar code 110 consisting of high marks 100, low marks 101 or spaces 102. Intersymbol interference may cause a code which consists of a high mark followed by a space to have a zero crossing 103 substantially overlapping into the bit period for the space. When the prior circuit detected that zero crossing 103 and corrected the reference clock due to the distortion and then readjusted at the end of the succeeding bit period 104 which is not distorted, the reference clock would jitter. Further, in a code which consists of a high mark then a space or a low mark then a space, as the signal swings from the mark to the zero level of the space there may be overshoot causing "ringing" which generates a series of very quick zero crossings 105. As the prior art circuit attempted to adjust the reference clock for each zero crossing, the reference clock would jitter.
An additional problem with the prior art phase-locked loop circuit is the size and energy consumption of the analog zero detector which is necessary in those circuits.
Thus, there is a need for an apparatus which will reduce clock jitter caused by intersymbol interference and "ringing" which causes multiple zero crossings. Further, there is a need for a circuit which will eliminate the large and inefficient analog zero crossing detector used by art prior devices.